1. Field of the Invention
This invention relates to integrated circuit (IC) testing technology, and more particularly, to a method and system for determining the fail patterns of fabricated wafers in an automated Wafer Acceptance Test (WAT).
2. Description of Related Art
In IC fabrication, there are many factors that affect the acceptance of the fabricated wafers. Therefore, a wafer is typically formed with some testing structures together with the internal circuitry of the wafer for the purpose of performing testing on the internal circuitry of the wafer. As a standard practice, fabricated wafers should undergo the what is known as a Wafer Acceptance Test (WAT) procedure to check whether they are acceptable. However, since each fabrication process produces a very great quantity of wafers, it is not feasible to perform the WAT procedure on all the fabricated wafers. Typically, only a number of randomly selected samples from each lot are tested. A WAT procedure typically includes a number of different test items performed separately on the selected samples, and the results from these test items are then analyzed by statistical methods to cover all the fabricated wafers in the lot.
A wafer is typically formed with a test fixture, called kerf-macro structure, in the kerf between the various dice in the wafer, which can be used to perform various test items on the wafer for the purpose of collecting parametric test data from the wafer. These parametric test data can help determine the health-of-line of the wafer fabrication process to judge whether the fabricated wafers are acceptable or not. These data can also help determine the problems in the fabrication process that cause the rejection so that the problems can be corrected.
The foregoing testing is performed on a randomly selected set of samples from all the fabricated wafers in each lot, and the results are then extended by statistical methods to cover all the fabricated wafers in the lot. However, since the amount of the test data is quite enormous, only a small portion thereof is used by the test engineer group for analysis. By conventional testing methods, since all the test items are analyzed individually rather than collectively from the fail patterns thereof, the results may be inadequate to point out some particular problems in the fabrication process.
As a summary, conventional testing methods have the following drawbacks. First, the test items are analyzed individually rather than collectively, so that the results may be inadequate. Second, it is impossible to perform analysis from the correlation of the test data with the fabrication equipment, fabricated wafers, and lots. Third, the use of the test data for analysis is inadequate.